1. Field of the Invention
The present invention relates generally to semiconductor integrated circuit devices, and more specifically, to a semiconductor integrated circuit device including a signal generation circuit for outputting a power-on reset signal.
2. Description of the Background Art
FIG. 1 is a block diagram showing a conventional semiconductor integrated circuit device including a power-on reset signal generation circuit. Referring to FIG. 1, the conventional semiconductor integrated circuit device 120 includes a power supply potential node 100 supplied with power supply potential Vcc, and a ground potential node 110 connected to the ground potential. Semiconductor integrated circuit 120 further includes a power-on reset signal generation circuit 121 receiving the power supply potential from power supply potential node 100, and outputting a power-on reset signal POR which rises to a prescribed potential in response to a rising of the power supply potential from the ground potential to a prescribed potential (5 V, for example) and falls to a low level (L level) after lapse of a prescribed time period.
Semiconductor integrated circuit device 120 further includes an internal circuit 123 driven by power supply potential Vcc supplied from power supply potential node 100 to process an input signal. Internal circuit 123 includes a processing circuit 123a. Processing circuit 123a has an output node 105, and the potential of the output attains an unstable state, if a signal input to processing circuit 123a is not active when the power supply potential rises from the ground potential.
Referring to FIG. 2, power-on reset signal generation circuit 121 includes a capacitor 121a connected between power supply potential node 100 and a first node 121b, a discharge transistor 121c formed of an n channel MOS (Metal Oxide Semiconductor) transistor connected between first node 121b and ground potential node 110, first and second inverters 121d and 121f connected between first node 121b and a POR output node 121e in an inverse-parallel manner and each driven by power supply potential Vcc from power supply potential node 100.
First inverter 121d and second inverter 121f use their own outputs as each other's inputs to constitute a flipflop circuit. The flipflop circuit has two stable states. In one stable state, the flipflop circuit holds an H level (high level) potential higher than a prescribed threshold voltage at first node 121b, and an L level (low level) potential substantially the same as the ground potential and lower than a prescribed threshold voltage at POR output node 121e. In the other steady state, the flipflop circuit holds the L level potential at first node 121b and the H level potential at POR output node 121e.
Power-on reset signal output circuit 121 further includes a third inverter 121g driven by power supply potential Vcc supplied from power supply potential node 100, and having an input connected to POR output node 121e and an output connected to POR output node 122, and a delay circuit 121h receiving a power-on reset signal POR from POR output node 122 and outputting a delay signal DPOR delayed from the power-on reset signal by a prescribed time period to the gate of discharge transistor 121c. Delay circuit 121h is for example a general delay circuit formed of a capacitor and a resistor.
One example of processing circuit 123a is illustrated in FIG. 3. Referring to FIG. 3, processing circuit 123a includes two NOR gates 123a1 and 123a2 constituting a flipflop circuit. NOR gate 123a1 has three inputs connected to an input node 123a3, POR output node 122, and the output of NOR gate 123a2, respectively. NOR gate 123a2 has two inputs connected to an input node 123a4 and the output of NOR gate 123a1, respectively. The potentials of output nodes 123a5 and 123a6 of NOR gates 123a1 and 123a2, respectively, attain an unstable state when the power supply potential rises from the ground potential.
In the flipflop circuit formed of NOR gates 123a1 and 123a2, the outputs on output nodes 123a5 and 123a6 are indefinite, when inputs from input nodes 123a3, 123a4, and POR output node 122 are all at the L level potential. More specifically, in this case, these outputs can take either the L level potential or the H level potential.
If an input from POR output node 122 is the H level potential, however, the potential of output node 123a5 attains the L level regardless of the value of input from either of input node 123a3 and 123a4. When an input to input node 123a4 is the L level potential as when power supply potential Vcc rises from the ground potential, the output of output node 123a6 becomes the H level potential.
Referring to a timing chart in FIG. 4, the conventional semiconductor integrated circuit device 120 shown in FIGS. 1 to 3 operates as follows at the time of power-up. As illustrated in FIG. 4(a), assume that power supply potential Vcc starts rising from the ground potential toward a prescribed potential at time t.sub.1. At this time, the input of input node 123a4 is the L level potential.
Referring to FIG. 4(b), the potential N1 of first node 121b rises following power supply potential Vcc through capacitor 121a. It is assumed that the potential N1 of first node 121b, as illustrated in FIG. 4(b), exceeds the threshold voltage of first inverter 121d at time t.sub.2. As illustrated in FIG. 4(c), until time t.sub.2, power supply potential Vcc is output as power-on reset inversion signal POR to POR output node 121e. At time t.sub.2, the potential N1 of first node 121b exceeds the threshold voltage of first inverter 121d. At time t.sub.2, power-on reset inversion signal POR output to POR output node 121e is substantially pulled to the ground potential. Note that power-on reset inversion signal POR is at a potential slightly higher than the ground potential near time t.sub.2, but does not exceed the threshold voltage of third inverter 121g at the time.
In response to power-on reset inversion signal POR, third inverter 121g outputs power-on reset signal POR to its POR output node 122. Power-on reset signal POR, as illustrated in FIG. 4(e), follows power supply potential Vcc and rises to the high level potential.
In response to power-on reset signal POR, the potential of an output node whose potential is indefinite when power supply potential Vcc rises is reset as follows. Note that, in this case, the potential IN1 of output node 123a5 is reset to the L level, and the potential IN2 of output node 123a6 is reset to the H level Vcc. The potential IN1 of output node 123a5 is, as illustrated in FIG. 4(f), reset to the L level at time t.sub.3. The potential IN2 of output node 123a6 is reset to the H level at time t.sub.4 as illustrated in FIG. 4(g).
Meanwhile, power-on reset signal POR is delayed by delay circuit 121h (see FIG. 2) by a prescribed time delay .DELTA.T and applied to the gate of discharge transistor 121c as a delay signal DPOR. Delay signal DPOR rises delayed from power-on reset signal POR by .DELTA.T as illustrated in FIG. 4(d), and exceeds the threshold voltage of discharge transistor 121c at time t.sub.5. It is noted that time t.sub.5 is later than time t.sub.2 by a period .DELTA.T.
Discharge transistor 121c conducts, and first node 121b and ground potential 110 are electrically connected. The potential N1 of first node 121b begins to fall to the L level potential as illustrated in FIG. 4(b) after time t.sub.5. Potential N1 reaches to the L level potential at time t.sub.6.
In response to the potential N1 of first node 121b falling to the L level potential, power-on reset inversion signal POR output to POR output node 121e rises. As illustrated in FIG. 4(c), power-on reset inversion signal POR exceeds the threshold voltage of third inverter 121g at time t.sub.6.
Power-on reset signal POR output to POR output node 122 from third inverter 121g falls substantially to the ground potential at time t.sub.7 as illustrated in FIG. 4(e). Delay signal DPOR output by delay circuit 121h falls substantially to the ground potential at time t.sub.8 as illustrated in FIG. 4(d). Discharge transistor 121c is turned off, and first node 121b is electrically isolated from ground potential node 110.
Upon usual turning on of the power supply, power-on reset signal generation circuit 121 applies power-on reset signal POR to processing circuit 123a as described above. In response to power-on reset signal POR, the internal state of processing circuit 123a and its output are reset. Power-on reset signal generation circuit 121 is also reset after a prescribed time period in response to delay signal DPOR delayed from power-on reset signal POR, and power-on reset signal POR output therefrom falls to the L level potential.
Assume that during a usual operation of semiconductor integrated circuit device 120 power supply potential Vcc instantaneously fails. In such a case, power supply potential Vcc becomes an L level potential during a period of about 100 ns-1 .mu.s from a prescribed potential and then once again rises. The operation of the conventional power-on reset signal generation circuit 121 and semiconductor integrated circuit device 120 in this case will be described.
Referring to FIG. 5(a), power supply potential Vcc which is usually H level potential falls to L level potential at time t.sub.10.
Referring to FIGS. 2 and 5(b), the falling of power supply potential is transmitted to first node 121b through capacitor 121a, and the potential N1 of first node 121b falls from a substantial ground potential (L level) to a minus level.
Since the potential N1 of first node 121b is equal to or smaller than the L level, power-on reset inversion signal POR output from first inverter 121d follows power supply potential Vcc as illustrated in FIG. 5(c) and falls from H level to L level potential at time t.sub.11.
Referring to FIG. 2, second inverter 121f tends to maintain the potential N1 of first node 121b at the ground potential until the potential of power-on reset inversion signal POR is equal to or smaller than the threshold voltage of inverter 121f. The potential N1 of first node 121b is however more affected by the negative potential provided from capacitor 121a. Accordingly, the potential N1 of first node 121b falls to about the potential of the inverse of a prescribed potential for usual power supply potential Vcc.
As illustrated in FIG. 5(a), at time t.sub.12 after the passage of time period 100 ns-1 .mu.m from time t10, power supply potential Vcc rises, and then potential N1 of first node 121b rises as illustrated in FIG. 5(b) affected by the rising of power supply potential Vcc through capacitor 121a. The potential N1 of first node 121b rises to a level slightly higher than a substantial ground potential (L level).
Referring to FIG. 5(c), power-on reset inversion signal POR output from first inverter 121d follows power supply potential Vcc and starts rising from L level potential to H level potential, since the potential N1 of first node 121b on the input side is still at the L level. At time t.sub.13, the potential of power-on reset inversion signal POR exceeds the threshold voltage of third inverter 121g.
Until time t.sub.13, as illustrated in FIG. 5(e), power-on reset signal POR output by third inverter 121b rises with the rising of power supply potential Vcc and attains the H level. When power-on reset inversion signal POR exceeds the threshold voltage of third inverter 121g at time t.sub.13, power-on reset signal POR falls to L level potential, and then to a substantial ground potential at time t.sub.14.
Signal DPOR delayed from power-on reset signal POR output from delay circuit 121h also rises to the H level potential at time t.sub.15 delayed from power-on reset signal POR by a time delay .DELTA.T as illustrated in FIG. 5(d), and then falls to L level potential.
Power-on reset signal POR output from the above-described conventional power-on reset generation circuit 121 is sometimes at the H level potential only during a short period of time, if power supply potential Vcc instantaneously fails. In such a case, power-on reset signal POR can fall before a resetting processing is surely performed in response to power-on reset signal POR in internal circuit 123 shown in FIG. 1. Uncertain resetting of the output node of processing circuit 123a results in subsequent erroneous operation in the processing circuit. Such a disadvantage needs to be overcome.